keo nha cai bet88 bet88 nhà cái Sending Bundled GPIO keo nha cai bet88 I2C with a Serial Transceiver: Two Changes with Significant User Benefits Explained
2023.08.22
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THine Electronics đã phát hành IC thu phát nối tiếp mới (IC thu phát SerDes), THCS253/THCS254, vào tháng 7 năm 2023. Biệt danh của nó là IOHA:B (phát âm là eye-oh-hab).
This article is keo nha cai bet88 second of a two-part series describing this new product. InPhần 1của loạt bài này, chúng tôi đã mô tả các tính năng mới của sản phẩm và giới thiệu những thay đổi so với THCS251/THCS252 trước đó, cụ thể là hỗ trợ I2C trên GPIO (I/O mục đích chung). sản phẩm mới này. Trong phần thứ hai này, chúng tôi muốn mô tả những thay đổi chi tiết hơn và giới thiệu một thay đổi khác: giới thiệu các chế độ đồng bộ/không đồng bộ.
This article is keo nha cai bet88 second of a two-part series describing this new product. InPhần 1của loạt bài này, chúng tôi đã mô tả các tính năng mới của sản phẩm và giới thiệu những thay đổi so với THCS251/THCS252 trước đó, cụ thể là hỗ trợ I2C trên GPIO (I/O mục đích chung). sản phẩm mới này. Trong phần thứ hai này, chúng tôi muốn mô tả những thay đổi chi tiết hơn và giới thiệu một thay đổi khác: giới thiệu các chế độ đồng bộ/không đồng bộ.
I/O có thể tùy chỉnh tự do
Chức năng chính của THCS253/THCS254 mới là thay thế đường truyền song song được gửi trên nhiều đường tín hiệu, bằng đường truyền nối tiếp chỉ sử dụng hai cặp đường vi sai. Ví dụ: 34 đường tín hiệu có thể giảm xuống chỉ còn bốn đường. sản phẩm mới của chúng tôi. Điều này giúp chúng tôi giảm đường dây lên tới 88%. Hơn nữa, điều này giúp giảm trọng lượng của cáp đi dây, cho phép mở rộng khoảng cách truyền dẫn. Như phần một của loạt bài này đã đề cập, lợi ích của những thay đổi này đối với người dùng là rất đáng kể.
However, these functions are identical to keo nha cai bet88 conventional THCS251/THCS252 model and are not new. Our new product inherits these basic functions from keo nha cai bet88 previous product while making two significant changes. These are I2C support in addition to GPIO, as mentioned at keo nha cai bet88 beginning of this article, and keo nha cai bet88 introduction of synchronous/asynchronous modes.
First, let us give you more details on keo nha cai bet88 first change in this model, I2C support and GPIO. keo nha cai bet88 meat of this change has already been briefly described in keo nha cai bet88 first article. In other words, in addition to multiple GPIOs, one I2C systems can be bundled together for serial transmission. This bundling gives users an extremely significant advantage. keo nha cai bet88 advantage is keo nha cai bet88 ability to customize keo nha cai bet88 I/O (input/output interface) with a high degree of freedom by rewriting internal registers using I2C.
THCS253
Hình 1 Cài đặt I/O mặc định (THCS253)
keo nha cai bet88 user may freely set keo nha cai bet88 number of these GPIs and GPOs. This flexibility stems from keo nha cai bet88 fact that each pin can be designated as a GPI or GPO by rewriting keo nha cai bet88 internal registers via I2C. Fig. 2 is a specific example of this phenomenon (an example in which each pin is assigned to a GPIO, I2S, SPI, or UART input/output).
keo nha cai bet88 conventional THCS251/THCS252 also allowed users to specify keo nha cai bet88 number of GPIs and GPOs; however, these conventional models only allowed a selection of four levels indicating keo nha cai bet88 ratio of keo nha cai bet88 number of GPIs and GPOs. In other words, keo nha cai bet88 degree of freedom to customize keo nha cai bet88 I/O section is lower with THCS251/THCS252 than in our new product.
Customizing keo nha cai bet88 I/O section is highly effective when sudden design changes occur, such as adding new functions to keo nha cai bet88 electronic equipment to be designed or when keo nha cai bet88 design must be standardized in preparation for future model changes or additional functions. When design changes, model changes, or additional functions are implemented, keo nha cai bet88 number of I/O pins may increase due to an increase in keo nha cai bet88 number of circuits that allow for new functions, or keo nha cai bet88 positioning of I/O pins may change. Conventional products did not allow a high degree of freedom in customizing keo nha cai bet88 I/O section, and in some cases, hardware, such as signal transmission paths, had to be redesigned. However, by adopting our new product, I/O can be customized with a high degree of freedom, allowing for highly flexible handling of design changes and additional functions. This flexibility gives users a higher chance of not needing to redesign hardware. This flexibility can help avoid situations where keo nha cai bet88 design period is extended and design costs increase.
However, these functions are identical to keo nha cai bet88 conventional THCS251/THCS252 model and are not new. Our new product inherits these basic functions from keo nha cai bet88 previous product while making two significant changes. These are I2C support in addition to GPIO, as mentioned at keo nha cai bet88 beginning of this article, and keo nha cai bet88 introduction of synchronous/asynchronous modes.
First, let us give you more details on keo nha cai bet88 first change in this model, I2C support and GPIO. keo nha cai bet88 meat of this change has already been briefly described in keo nha cai bet88 first article. In other words, in addition to multiple GPIOs, one I2C systems can be bundled together for serial transmission. This bundling gives users an extremely significant advantage. keo nha cai bet88 advantage is keo nha cai bet88 ability to customize keo nha cai bet88 I/O (input/output interface) with a high degree of freedom by rewriting internal registers using I2C.
THCS253
keo nha cai bet88 user may freely set keo nha cai bet88 number of these GPIs and GPOs. This flexibility stems from keo nha cai bet88 fact that each pin can be designated as a GPI or GPO by rewriting keo nha cai bet88 internal registers via I2C. Fig. 2 is a specific example of this phenomenon (an example in which each pin is assigned to a GPIO, I2S, SPI, or UART input/output).
Hình 2 Tùy chỉnh I/O bằng cách viết lại các thanh ghi nội bộ
keo nha cai bet88 conventional THCS251/THCS252 also allowed users to specify keo nha cai bet88 number of GPIs and GPOs; however, these conventional models only allowed a selection of four levels indicating keo nha cai bet88 ratio of keo nha cai bet88 number of GPIs and GPOs. In other words, keo nha cai bet88 degree of freedom to customize keo nha cai bet88 I/O section is lower with THCS251/THCS252 than in our new product.
Customizing keo nha cai bet88 I/O section is highly effective when sudden design changes occur, such as adding new functions to keo nha cai bet88 electronic equipment to be designed or when keo nha cai bet88 design must be standardized in preparation for future model changes or additional functions. When design changes, model changes, or additional functions are implemented, keo nha cai bet88 number of I/O pins may increase due to an increase in keo nha cai bet88 number of circuits that allow for new functions, or keo nha cai bet88 positioning of I/O pins may change. Conventional products did not allow a high degree of freedom in customizing keo nha cai bet88 I/O section, and in some cases, hardware, such as signal transmission paths, had to be redesigned. However, by adopting our new product, I/O can be customized with a high degree of freedom, allowing for highly flexible handling of design changes and additional functions. This flexibility gives users a higher chance of not needing to redesign hardware. This flexibility can help avoid situations where keo nha cai bet88 design period is extended and design costs increase.
Bộ lọc và định dạng đầu ra có thể tùy chỉnh
Ngoài ra, người dùng có thể định cấu hình định dạng đầu ra và bộ lọc nhiễu kỹ thuật số bằng cách viết lại các thanh ghi bên trong sử dụng I2C. Có sẵn hai tùy chọn định dạng đầu ra: bộ lọc nhiễu kỹ thuật số và cống mở. người dùng cũng có thể chọn số bước lọc (thứ tự bộ lọc). Tuy nhiên, không thể đặt số bước (thứ tự bộ lọc) cho mỗi thiết bị đầu cuối. Ví dụ: nếu người dùng quyết định ba bước (thứ tự thứ ba), thì bước lọc. (thứ tự lọc) áp dụng cho mỗi thiết bị đầu cuối sẽ là bước thứ ba (thứ tự thứ ba).
Sử dụng cả chế độ đồng bộ và không đồng bộ
Tiếp theo, chúng tôi thảo luận về một thay đổi quan trọng khác: giới thiệu các chế độ đồng bộ/không đồng bộ. Sản phẩm thông thường của chúng tôi, THCS251/THCS252, chỉ có thể được sử dụng ở chế độ đồng bộ, nhưng sản phẩm mới của chúng tôi có thể được sử dụng ở cả chế độ đồng bộ và không đồng bộ. chọn chế độ trong cài đặt thiết bị đầu cuối chip thứ cấp.
Synchronous mode is when keo nha cai bet88 downlink from keo nha cai bet88 primary chip to keo nha cai bet88 secondary chip and keo nha cai bet88 uplink from keo nha cai bet88 secondary chip to keo nha cai bet88 primary chip operate with keo nha cai bet88 same reference clock signal. In other words, synchronous mode is when keo nha cai bet88 frequency and phase of keo nha cai bet88 downlink and uplink reference clock signals are precisely keo nha cai bet88 same. In practice, keo nha cai bet88 synchronous mode is when keo nha cai bet88 uplink is operated by receiving a serial signal (Clock embedded 8B10B encoding signal) sent from keo nha cai bet88 primary chip and using keo nha cai bet88 clock signal extracted by keo nha cai bet88 clock data recovery (CDR) circuit in keo nha cai bet88 secondary chip (Fig. 3 and Fig. 4).
Hình 3 Ví dụ về chế độ đồng bộ (với đầu vào bên ngoài)
Hình 4 Ví dụ về chế độ đồng bộ (đối với OSC bên trong)
On keo nha cai bet88 other hand, asynchronous mode is when keo nha cai bet88 downlink and uplink operate with different reference clock signal (Fig. 5 and Fig. 6). Even if keo nha cai bet88 frequency of both reference clock signals is keo nha cai bet88 same, if keo nha cai bet88 phases are different, it will be asynchronous mode.
Hình 5 Ví dụ về chế độ không đồng bộ (với đầu vào bên ngoài)
Hình 6 Ví dụ về chế độ không đồng bộ (đối với OSC nội bộ)
One advantage of synchronous mode is that it does not require a reference clock signal source to be supplied to keo nha cai bet88 secondary chip. However, there are some disadvantages. keo nha cai bet88 primary chip is keo nha cai bet88 only one of keo nha cai bet88 chips that can implement synchronous sampling of parallel signals. For keo nha cai bet88 secondary chip, keo nha cai bet88 reference clock signal used is extracted by keo nha cai bet88 CDR circuit and is unrelated to keo nha cai bet88 parallel signal to be captured, resulting in oversampling. A downlink with synchronous sampling can transmit high-speed image/video signals. In contrast, an uplink with oversampling cannot send high-speed image/video signals and can only transmit low-speed control signals.
Asynchronous mode was introduced to eliminate this disadvantage. Separate reference clock signals can be provided for keo nha cai bet88 primary and secondary chips, allowing synchronous sampling of parallel signals on both. In other words, high-speed image/video signals can be sent through downlink and uplink.
There is one point to note here, however—keo nha cai bet88 question being keo nha cai bet88 method of supplying keo nha cai bet88 reference clock signals to keo nha cai bet88 primary and secondary chips. There are two supply methods. keo nha cai bet88 first of these is to supply keo nha cai bet88 reference clock signal from an external clock signal circuit. keo nha cai bet88 other method is to supply keo nha cai bet88 signal from keo nha cai bet88 clock oscillation circuit (internal OSC) built into each chip. keo nha cai bet88 former can allow common use together with keo nha cai bet88 reference clock of keo nha cai bet88 parallel signal to enable synchronous sampling. However, keo nha cai bet88 latter cannot allow common use with keo nha cai bet88 reference clock signal of keo nha cai bet88 parallel signal because keo nha cai bet88 internal OSC clock signal cannot be output externally, resulting in oversampling. Therefore, users need to select a reference clock signal supply method that matches keo nha cai bet88 characteristics of keo nha cai bet88 signals they wish to transit in keo nha cai bet88 downlink and uplink.
Synchronous mode is when keo nha cai bet88 downlink from keo nha cai bet88 primary chip to keo nha cai bet88 secondary chip and keo nha cai bet88 uplink from keo nha cai bet88 secondary chip to keo nha cai bet88 primary chip operate with keo nha cai bet88 same reference clock signal. In other words, synchronous mode is when keo nha cai bet88 frequency and phase of keo nha cai bet88 downlink and uplink reference clock signals are precisely keo nha cai bet88 same. In practice, keo nha cai bet88 synchronous mode is when keo nha cai bet88 uplink is operated by receiving a serial signal (Clock embedded 8B10B encoding signal) sent from keo nha cai bet88 primary chip and using keo nha cai bet88 clock signal extracted by keo nha cai bet88 clock data recovery (CDR) circuit in keo nha cai bet88 secondary chip (Fig. 3 and Fig. 4).
On keo nha cai bet88 other hand, asynchronous mode is when keo nha cai bet88 downlink and uplink operate with different reference clock signal (Fig. 5 and Fig. 6). Even if keo nha cai bet88 frequency of both reference clock signals is keo nha cai bet88 same, if keo nha cai bet88 phases are different, it will be asynchronous mode.
One advantage of synchronous mode is that it does not require a reference clock signal source to be supplied to keo nha cai bet88 secondary chip. However, there are some disadvantages. keo nha cai bet88 primary chip is keo nha cai bet88 only one of keo nha cai bet88 chips that can implement synchronous sampling of parallel signals. For keo nha cai bet88 secondary chip, keo nha cai bet88 reference clock signal used is extracted by keo nha cai bet88 CDR circuit and is unrelated to keo nha cai bet88 parallel signal to be captured, resulting in oversampling. A downlink with synchronous sampling can transmit high-speed image/video signals. In contrast, an uplink with oversampling cannot send high-speed image/video signals and can only transmit low-speed control signals.
Asynchronous mode was introduced to eliminate this disadvantage. Separate reference clock signals can be provided for keo nha cai bet88 primary and secondary chips, allowing synchronous sampling of parallel signals on both. In other words, high-speed image/video signals can be sent through downlink and uplink.
There is one point to note here, however—keo nha cai bet88 question being keo nha cai bet88 method of supplying keo nha cai bet88 reference clock signals to keo nha cai bet88 primary and secondary chips. There are two supply methods. keo nha cai bet88 first of these is to supply keo nha cai bet88 reference clock signal from an external clock signal circuit. keo nha cai bet88 other method is to supply keo nha cai bet88 signal from keo nha cai bet88 clock oscillation circuit (internal OSC) built into each chip. keo nha cai bet88 former can allow common use together with keo nha cai bet88 reference clock of keo nha cai bet88 parallel signal to enable synchronous sampling. However, keo nha cai bet88 latter cannot allow common use with keo nha cai bet88 reference clock signal of keo nha cai bet88 parallel signal because keo nha cai bet88 internal OSC clock signal cannot be output externally, resulting in oversampling. Therefore, users need to select a reference clock signal supply method that matches keo nha cai bet88 characteristics of keo nha cai bet88 signals they wish to transit in keo nha cai bet88 downlink and uplink.
Nâng cao khả năng sử dụng của chức năng chờ
Cuối cùng, chúng tôi sẽ giới thiệu ba chức năng mới hữu ích được thực hiện bằng I2C do sản phẩm mới của chúng tôi mang lại.
keo nha cai bet88 first is keo nha cai bet88 PWM signal generation function (Fig. 7). In conventional products, it was possible to input PWM signals with a frequency that allowed oversampling via GPIOs in keo nha cai bet88 primary chip, bundle them into serial signals, and send them to keo nha cai bet88 secondary chip. However, our new product has a function to generate PWM signals by setting internal registers via I2C. These signals can be generated on a primary chip or a secondary chip. This PWM signal generation function can adjust keo nha cai bet88 brightness of LCD panel backlights, control keo nha cai bet88 dimness of LEDs, drive motors, and be used for other uses.
keo nha cai bet88 second is keo nha cai bet88 I/O expander function (Fig. 8). This function converts data between I2C and GPIO and sends it to keo nha cai bet88 primary or secondary chip. keo nha cai bet88 function can convert I2C serial data into GPO parallel data and send it, or monitor parallel data input to GPI, store keo nha cai bet88 result in an internal register, and output it as serial data from I2C. We call this keo nha cai bet88 I/O expander function because it looks as though keo nha cai bet88 I2C pins are expanded.
keo nha cai bet88 third is keo nha cai bet88 standby function (Fig. 9). In our new product, keo nha cai bet88 internal registers can be rewritten via I2C to enter or leave a standby state. keo nha cai bet88 primary chip can set keo nha cai bet88 transition to/from a standby state for keo nha cai bet88 primary chip and keo nha cai bet88 secondary chip.
Electric current consumption in standby mode is low, at 6 mA. Normal operation sees this consumption go up to 50 to 100 mA. I2C and 8-bit GPIOs can be exchanged between keo nha cai bet88 primary and secondary chips, even in standby mode. Furthermore, even in standby mode, optical transmission through a photoelectric conversion device and wireless transmission through short-distance wireless communication devices can continue. Thus, keo nha cai bet88 system can switch from normal operation to standby without breaking keo nha cai bet88 link.
End
keo nha cai bet88 first is keo nha cai bet88 PWM signal generation function (Fig. 7). In conventional products, it was possible to input PWM signals with a frequency that allowed oversampling via GPIOs in keo nha cai bet88 primary chip, bundle them into serial signals, and send them to keo nha cai bet88 secondary chip. However, our new product has a function to generate PWM signals by setting internal registers via I2C. These signals can be generated on a primary chip or a secondary chip. This PWM signal generation function can adjust keo nha cai bet88 brightness of LCD panel backlights, control keo nha cai bet88 dimness of LEDs, drive motors, and be used for other uses.
Hình 7 Chức năng tạo tín hiệuPWM
keo nha cai bet88 second is keo nha cai bet88 I/O expander function (Fig. 8). This function converts data between I2C and GPIO and sends it to keo nha cai bet88 primary or secondary chip. keo nha cai bet88 function can convert I2C serial data into GPO parallel data and send it, or monitor parallel data input to GPI, store keo nha cai bet88 result in an internal register, and output it as serial data from I2C. We call this keo nha cai bet88 I/O expander function because it looks as though keo nha cai bet88 I2C pins are expanded.
Hình 8 chức năng mở rộng I/O
keo nha cai bet88 third is keo nha cai bet88 standby function (Fig. 9). In our new product, keo nha cai bet88 internal registers can be rewritten via I2C to enter or leave a standby state. keo nha cai bet88 primary chip can set keo nha cai bet88 transition to/from a standby state for keo nha cai bet88 primary chip and keo nha cai bet88 secondary chip.
Hình 9 Chức năng chờ
Electric current consumption in standby mode is low, at 6 mA. Normal operation sees this consumption go up to 50 to 100 mA. I2C and 8-bit GPIOs can be exchanged between keo nha cai bet88 primary and secondary chips, even in standby mode. Furthermore, even in standby mode, optical transmission through a photoelectric conversion device and wireless transmission through short-distance wireless communication devices can continue. Thus, keo nha cai bet88 system can switch from normal operation to standby without breaking keo nha cai bet88 link.
End
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- Bộ thu phát nối tiếp cho GPIO và I2C - Phim khái niệm IOHA:B
- Giải pháp đơn giản cho các vấn đề I/O không cần FGPA: Bộ thu phát nối tiếp kết hợp và gửi tín hiệu GPIO và I2C hiện đã có sẵn!